As part of traditional test of digital systems, logic and protocol analyzers collect synchronous digital data from a target system in order to test and verify proper system operation. The analyzers typically store samples from the target system using a sample clock source derived from a clock that drives the target system or a source encoded as part of the target system data stream. The analyzer provides time stamping with each stored sample in order to time correlate each stored sample. In one conventional system, the time stamp is an absolute count based upon a high frequency time clock that is stored with each sample taken. The timing resolution of the time stamp is limited by the frequency of the time clock and the amount of memory available to store the time stamp. As can be appreciated, the higher the clock frequency, the better the timing resolution, and the more memory required to store the necessary information.
In another traditional system that makes more efficient use of system memory, a store qualification sampling method stores only samples that meet some user defined criteria. The time stamp is based upon the sample clock and reflects a count of the number of states that are not stored. The time clock calculates an average period of the sample clock to a desired resolution. Based upon the assumption that the calculated average period of the sample clock is constant over time, the timing between stored samples can be calculated from the number of sample clock transitions that occur between stored samples.
As clock frequencies increase, the electronics that they run are more prone to radiate and it is more difficult to pass electromagnetic interference (“EMI”) specifications. To mitigate EMI and to remain compliant with the EMI requirements, some digital systems use spread spectrum clocking (“SSC”). SSC modulates the clock frequency just enough to spread the radiation power spectrum over a wider frequency band to reduce the power amplitude at any one frequency. A typical modulation is 0-0.5% at a 30 kHz rate. Therefore, for some digital systems, the sample clock period against which a time gap may be calculated is not constant and the timing calculation that uses an overall average of the sample clock period as in the traditional system includes an error term. When accumulated over a range of samples, the error term can be significant when compared to the resolution of the time clock. Accordingly, the traditional sample clock count accumulation method of measuring the time gap between samples and calculating the time gap against an average measured sample clock period yields unacceptably erroneous measurements.
There is a need, therefore, for an improved method and apparatus for collecting digital data for a target system that uses spread spectrum clocking.